EE-Training

Knowledge makes you Curious

Using Cadence SigXplorer for Parallel Termination

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Some of the EE-Training courses use the Cadence SigXplorer tool, which is a very handy IBIS*) simulator. I have previously written about other similar tools like the simulator-part of Altium and Mentor’s Hyperlynx. It’s not really important what tool you use, it’s more how you use it and what you do with the results. IBIS… Read more

High Speed Via

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How do you make high-speed vias that work at +56Gpbs? Recently a question came up: How big the clearance hole (anti-pad) needed to be for a through-hole via to have acceptable performance with 56Gbps signals on a high layer count board (22 layers / 2.4mm thickness). I decided to compile all the information I had… Read more