A question came up: Does the Zedboard bypass scheme make sense? The Zedboard is an eval board for the Xilinx Zynq-7000 FPGA. As such it may be nothing special, but when you look at the board you will notice a very interesting pattern of bypass capacitors. And there is a long story on the web page about why the designer thinks this is a good way to do bypass that way for a board like this.
Decoupling power supply is one of the most important topics in signal integrity, so I found this to be an interesting board with a good story. Do you agree with the method used? Is the designer right? Or is it BS? Would you be able to make that distinction if this was in an application note?
I invite your comments below.
PS: If you sign up before the early bird 10% discount on The Nordic SI Week 2014 with Lee Ritchey ends on March 1st, you may win one of these boards. Thanks to Silica for sponsoring this.
UPDATE (Jan 24, 14): I got the board in my hands now, so I could shoot some better pictures of this board from both the top and bottom side.
UPDATE: The results are in. Read about the measurements we did on this funky Zedboard bypass/decoupling capacitor scheme.