UPDATE: This content is now part of the 3-day SI course
PCB Stackup Design
Today’s high-speed PCBs, with their inherent signal integrity and power delivery requirements, make it necessary to employ far more discipline in the choice of materials and the arrangement of layers in the stackup. These requirements are outside the skill set of most PCB fabricators.
The objective of this course is to guide the design engineer through the process of evaluating and selecting the right laminate for any given design and then designing a PCB stackup that meets the numerous requirements of a complex, multilayer board that works right the first time. It discusses in detail the three methods of laminating printed circuit boards: Cap lamination, foil lamination and build up lamination, and how each fills a particular performance need.
Get access to new test data.
Lee has been doing new measurements on custom test boards and share this information in these classes. This is a unique knowledge/experience that more than pays for the course.
Knowledge of how to optimize the PCB stackup has become ever more critical as differential signal paths are approaching 32 Gb/S with higher speeds likely to be required in the near future.
Fast Data Paths
The fast data paths that are pervasive in all PCB products being currently designed to make it imperative to be able to design stackups that have predictable and repeatable impedances. This new seven-hour training session addresses several industry-critical issues including:
- Accounting for copper roughness and its effect on overall signal loss
- Specifying copper roughness to ensure repeatable loss from lot to lot and fabricator to fabricator
- Specifying glass weave styles to minimize differential skew
- Determining plane copper thickness to ensure power delivery needs are met
- Specifying dielectric materials that are readily available and economical to manufacture
- Creating stackups that can be successfully prototyped in the US or Europe and manufactured in Asia
- Deciding whether to use cap lamination, foil lamination, mass lamination or build up lamination
PCB Materials & Manufacturing
The class begins with a thorough treatment of how laminates are manufactured as well as those that are readily available at most fabricators around the world. Included in this section is measured loss tangent, dielectric constant and potential for weave induced skew, all information vital to success with the signal speeds in products currently under design.
It progresses to how PCBs are fabricated and on to the possible ways in which the layers of a PCB can be arranged to balance the needs of power delivery and signal integrity.
It examines which parameters in the impedance equation have the largest effect on impedance and methods to reduce impedance variation in production size lots of PCBs.
FAQ: How is this different from the 3|4-day course?
In the “Lee Ritchey: Signal Integrity” class, we spend about 1/2 hour on stackup design and materials as that is about all the time there is for this topic.
The one-day stackup class has far more info on stackup design and materials especially as they pertain to very high-speed signaling. All engineers who are dealing with multi-gigabit per second signaling will find this of great value.
Learn to Optimize Material Selection and Fabrication Techniques for Manufacturability, Reliability and Signal Integrity
Successful fabrication of any PCB starts with selecting the right laminate materials and creating a stackup design that works. Today’s high-speed PCBs with their inherent signal integrity and power delivery requirements make it necessary to employ far more discipline in the choice of materials and the arrangement of layers in the stackup. These requirements are outside the skill set of all PCB fabricators.
The objective of this course is to guide the design engineer through the process of evaluating and selecting the right laminate for any given design and then designing a PCB stackup that meets the numerous demands of a complex, multilayer board that works right the first time.
The demands addressed in this course include:
The following topic areas will be covered:
This course is designed for all the participants in the design and fabrication process. Among those who will find it valuable are:
Any engineering professional who works with high-speed design will understand the materials presented. No advanced mathematics are required.
Lee Ritchey is considered to be one of the industry’s premier authorities on high-speed PCB and system design and fabrication. He has participated in the design of more than 4,000 high-speed PCBs ranging from PC motherboards and elevator controllers to the backplanes used in terabit routers. He is currently involved in the design of several supercomputer class products as well as video games and servers of all kinds. The course draws substantially from this real-time experience with state of the art components, fabricators and materials. It also draws heavily on the design of backplanes and daughter boards containing thousands of 2.4, 4.8 and 9.6 GB/S signal paths.
In 2004, Ritchey was a regular columnist for EE Times and he has written many articles on high-speed design for trade publications such as EDN, Circuitree, and PC Design. He is the author of the books, “Right the First Time, A Practical Handbook on PCB and System Design, Volume 1 and Volume 2”, published by Speeding Edge.
This is what you get when you take this course:
- A full day of expert training 9:00 to 16:00 interchanging between theory, examples, and demonstrations with relevant design tools
- Binder with all course slides.
- A large collection articles for further reading (download archive provided at the course)
- Coffee/the/water + fruit, pastries, and a full lunch
- Signed course certificate
Where it isTo be announced
Copenhagen SI Week
Lee Ritchey: Signal Integrity day 1 (9:00-16:00)
|Tue||Lee Ritchey: Signal Integrity day 2 (9:00-16:00)|
|Wed||Lee Ritchey: Signal Integrity day 3 (9:00-16:00)|
|Thu||Simulation: Signal Integrity day 4 (9:00-16:00)|
|Fri||Lee Ritchey: Stackup Design day 5 (9:00-16:00)|