Design FPGA like a pro: Faster, easier and with better quality with advanced VHDL verification
Learn how to significantly reduce FPGA development time and system integration time. Avoid costly delays due to FPGA design, verification or documentation quality issues with this best practices course.
If your FPGA projects have any of these problems, you should take this course:
- Delays or spending more man-hours than scheduled
- Bugs appearing after completion
- Detecting bugs late in the project
- Last phase of development takes longer than anticipated
- Unstructured test benches for complex systems
- Timing or clock domain crossing problems
The benefit for your company and the entire team when you follow industry best practices as taught in this course are both better design quality and less time wasted in integration, debug and simulation. You will end up shipping better products faster. And you may even feel better about shipping, knowing you worked like a pro.
Content: Advanced VHDL Verification
This course is packed with relevant and pragmatic Best Practices for FPGA development. It is complementary to the courses for tools, technologies, design/verification languages and digital design from Altera, Xilinx, Aldec, Mentor, Esperan, Doulos, etc. They all have excellent courses for their target groups, but this course is unique in its focus on design practices for better quality products and more efficient projects.
The total course has the following approximate split on main subjects
- 35% Design – architecture, structure, issues, coding
- 25% Verification – architecture, structure, methodology
- 20% Clocking, Clock Domain crossing, Resets and Timing
- 10% Reuse and design for reuse
- 10% Quality assurance – at the development level
Mostly language independent, but examples are shown for VHDL.
More about the course is available in this presentation.
The feedback from previous courses has been very good. You can find the result of the evaluation of the previous Advanced VHDL Verification course in Stockholm in November 2014 here.
|Venue:||To be announced|
|Time:||10:00 to 16:30 on 1st day|
9:00 to 16:30 on 2nd day
8:30 to 15:30 on 3rd day
|Price:||To be announced|
Note: We start late and finish early, so you may save a hotel night and arrive on the morning of the 1st day.
Course language is English. Espen will take questions off-line in Norwegian, Danish and Swedish as well.
- Expert training three days
- Comprehensive course material (handed out after the course)
- Coffee/tea/water + fruit, pastries, and a full lunch
- Signed course certificate
- A limit of 20 participants
The instructor is Espen Tallaksen, who runs Bitvis in Norway. A well-respected design company focused on FPGA development. Very competent people. The course is also very well established and has been held many times before in Denmark/Norway and Sweden.
Espen has 25 years of digital, FPGA and ASIC design and methodology experience from companies like Kongsberg, Philips Semiconductors (Zurich), Nordic Semiconductor, Digitas and Data Respons.
To be announced.
Check out the Bitvis website for possible current courses, or go to the Doulos website for other similar topics – or contact us for more options.