Ground vias around signal via

There has long been a debate going on in the SI community on the need (or not) for ground vias or “stitching vias” near signal vias for high-speed signals. These days you can follow a very interesting and well-behaved debate on the SI-LIST email reflector about just this issue:

http://www.freelists.org/post/si-list/AW-Ground-vias-around-signal-via,21

Reading between the lines and balancing the arguments and data provided combined with personal experience from practical design work and my knowledge about the people debating this, I think the conclusion still holds that:

If you have a solid PDN design with low impedance across frequencies,

and

if you have roughly a 1 inch grid of Gnd/Vcc vias (which you will have more or less automatically from bypass caps, IC’s etc),

you do not need to place additional ground vias / “return path vias” / “stitching vias” near signal vias at least up to 28 GBps signaling as used by modern FPGA’s etc.

I am following the debate to see if I can see solid proof that this does not hold. Also, read about high-speed vias here.

Lots of boards I have been involved in are doing just fine without any ground vias around the signal vias. When you think about it, it’s not a big surprise these vias are not helping the return path impedance for the higher frequencies. Basically the inductance creates an impedance of 1/(2*pi*f*L) and the capacitive effect (parasitic or intended) creates an impedance of 2*pi*f*C. As we go up in frequency, the capacitive return path wins and easily gets to a low enough impedance. Adding a ground via is simply not effective at the higher frequencies.

The inductance of a via is a bit less than 1nH per mm the signal has to travel. Even with a thin pre-preg/laminate of 0.1mm, this is about 1/(2*pi*14GHz*0.1nH) = 2 mOhm. A 1pF capacitance will give an impedance in the same order of magnitude. The area needed at that spacing to form a capacitor of around 1pF is in the range of 2x2mm.

Let me hear your take on this?