Seminar: PCIe PHY Test

Are you developing hardware e. g. for an “Embedded Computer System”?

No matter which processor platform: High-Speed serial interfaces like PCIe, SATA or USB are an important part of your design! Implementing according to design guide rules is one thing. But how good is the design really? Physical Layer tests are required to judge the quality of the design. The scope vendors promise a one push button solution to verify the compliance to the standard. But one should judge these results carefully. Without understanding the methodology of the test errors could be made in the setup and also the scopes compliance application can have faulty routines.

Many designers don’t care as long the report shows a green “PASS” somewhere. But understanding the concept behind the executed tests is required to find potential weaknesses or, even more, important analyze the system in case of a “FAIL”.

The specification only gives numbers and the MOI (Method of Implementation) only describes how these numbers are measured.

But the real question is: WHAT is measured and WHY is it measured this way?

Content

• System Board Transmitter Tests Gen1/2
• System Board Receiver Test Gen1/2
• Gen3 RX/TX testing
• BER: Bit Error Rate
• Compliance test vs. Training Sequences
• Clock compliance test
• Jitter: Dual Dirac and TIE (Time Interval Error)
• Testing of Systems with solder down devices
• 8b/10b or 128/130b coding?
• Testing limits for Systems with or without Crosstalk?
• Clock Recovery?
• Data Clocked or Common Clocked?

Course language is English. Hermann will take questions and off-line discussions in German as well.

Please Note:  It is highly recommended that you have executed the test at least once on your own, before visiting the PCIe PHY Test Seminar.

Practical Details

Instructor

Hermann Ruckerbauer is a consultant and owner of EyeKnowHow. Before founding EyeKnowHow, Hermann worked with dynamic memory design at Qimonda AG, Infineon Technologies and Siemens/Infineon for many years.