• Skip to primary navigation
  • Skip to main content
  • Skip to primary sidebar
  • Skip to footer

EE-Training

Knowledge makes you Curious

  • Home
  • Training Courses
    • Signal Integrity to 56+Gbps with Hands-On Simulation
    • Open the Black Box of Memory
  • References
    • References for Signal Integrity with Hands-On Simulation
    • References for SI Simulation Workshop
    • References for Lee Ritchey: Signal Integrity
    • References for Lee Ritchey: Stackup Design
  • Blog
  • About
    • Terms & Conditions
    • VAT Refund
    • Jobs
  • Contact
You are here: Home » Blog » Simulation

Altium Signal Integrity Tool – Part II

September 3, 2012 by Rolf Ostergaard

In part I of this series of comparisons I started my quest to figure out if Altium is any good for SI analysis. It’s clearly one of the cheapest tools out there that allows you to do IBIS model-based simulations. Forgetting the price, can it get the job done?

Last time I did a very simple reflection analysis of one 74ALVC244 (tri-statable) output driving an input of the same type device. Now it’s maybe time to look at the results and see if we really need termination resistors for this.

Let’s repeat the input voltage waveform from the simulator. Here showing the results from Cadence, but the Altium curves were very similar.

Cadence simulation resultLooking at the waveform it becomes clear that a termination resistor could make this look a lot nicer. But is it really needed? Let’s look at the datasheet.

The Vi input voltage range is -0.5V to 4.6V. Looking at the simulated curve that seems to be exceeded a bit in the low end with the input voltage going down to -0.7V with the input diode clearly clamping. But look at the note (2) allowing this, provided the clamp current is within the listed limits. So in order to asses this we should really be simulating the current flowing into the input.

This is easy to do with Cadence SigExplorer – look:

And the results showing the input currents assure us that the allowed 50mA is not exceeded:

How to do this in Altium? No clue. This is Cadence.

How can we do this in Altium? Honestly, I have no clue how or if this is possible. Do you have any idea how to do this? Please let me know.

Now, this was a lot of work on the low state – how about the high state?

The upper input voltage limit from the absolute maximum rating section of the datasheet of 4.6V also seems to be exceeded quite a bit for both the TYP and FAST corners. So right there I know that there is really no way around finding a good termination scheme.

Conclusion

Simulations to observe input current does not seem to be possible with Altium. For that, you need a better tool.

Watch this space as the story continues in part III.

PS: Note that I will be happy to continue my exploration of Altium SI features if someone will lend me a license for a while… :-)

Q: How do you simulate the input current in Altium like shown for Cadence? Or is this completely irrelevant for you?

Share this:

  • Click to email a link to a friend (Opens in new window) Email
  • Click to share on LinkedIn (Opens in new window) LinkedIn
  • Click to share on Reddit (Opens in new window) Reddit
  • Click to share on Bluesky (Opens in new window) Bluesky

Filed Under: Simulation Tagged With: Altium, Cadence, SI, SigExplorer, Simulation, Tools

About Rolf Ostergaard

Rolf V. Ostergaard, M.Sc.EE. has worked with signal integrity in many different projects since working for 3Com in 1998 as a colleague to Lee Ritchey in Silicon Valley. While building a consulting business focused on advanced electronics and embedded software in Denmark, Rolf has been helping numerous companies with signal integrity and power integrity both as design, simulations, coaching, measurements, and troubleshooting. He started conducting training in SI in 2004 and has trained hundreds of engineers, which lead to founding EE-Training to further expand this.
You can hire Rolf to do signal integrity training and consulting worldwide and remote.

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Get a free SI book

Right the First Time
by Lee Ritchey (was $95),
and news from EE-Training

Subscribe below!

Search

PDNTool

Try pdntool.com and see how a 1-click optimizer might reduce your bypass caps. Read more...

Categories

Latest News

  • The ultimate memory interface training course live in Copenhagen June 2-4, 2025
  • How we got un-hacked
  • Free IBIS Simulator: KiCAD 8?
  • Online memory course: Mar 1-5, 2021
  • Crosstalk video demonstration for stripline
  • University SI Course – COVID’19 Version
  • Video: Using a Network Analyzer as a TDR
  • Video: PDN Measurement with a Network Analyzer
  • Signal Integrity w/ Hands-On NOW ONLINE May 11, 2020
  • Schmartboard breakout prototyping PCB

Recent User Comments

  • Noelia Scotti on Free IBIS Simulator: KiCAD 8?
  • Vikram Mane on Free IBIS Simulator: KiCAD 8?
  • Peter on Ground bounce demonstration board
  • Rolf Ostergaard on High Speed Via
  • Rolf Ostergaard on Video: PDN Measurement with a Network Analyzer

Contact

EE-Training
Rolf V. Ostergaard
+45 2684 4876
Denmark

QUOTES

“Training worth attending more than pays for itself in added value for you and your project”

“Training is expensive. Good training is even more expensive. No training is the most expensive.”

Rolf V. Ostergaard

M.Sc.EE, SI Consultant
Twitter: @rolfostergaard
LinkedIn: Profile
Resume: CV (pdf)

Copyright 2025. All prices shown are exclusive of VAT. General Terms & Conditions apply.
By using this site with cookies enabled in your browser you consent. Privacy policy. CSR policy.