Signal integrity experts have taught us to design power distribution systems that can support all devices on the board with a low low impedance up to a high “target PDN frequency”.
We all know, trust or believe that is important. But we soon realize that achieving low impedance from DC to infinity is impossible.
So how can we work with a specification like this one:
- No mention of the frequency range for the supply voltage requirement(1)
- The datasheet contains no information on the worst-case current consumption rate of change
Note 1: I recognize that this is “recommended” operating conditions, but given the fact that there are no other “guaranteed to work if you do this” data available this becomes a de’facto requirement for the designer.
Unknown PDN frequency range
So what we have is a device, pulling in current in an unknown frequency range, and we have to keep the voltage within the +/- 4-5%.
Usually, this is done with a combination of a power regulator and a set of bypass capacitors. The power regulator is limited in frequency by the frequency response of the feedback loop.
And capacitors work like this: If you pull out current, the voltage drops. This is dominated by 3 effects:
- Limited capacity. Pulling out 1A in 1s will remove 1 Q (Coulomb). The capacitor voltage will drop according to V = Q / C
- Non-zero ESR. Pulling out 1A from a 0.1 ohm ESR capacitor will lower the voltage 0.1V as given by V = I * R
- Non-zero ESL. Changing the current through a capacitor will change the voltage as given by V = L * di/dt
Impossible, so what do we do?
Without knowing di/dt, the design problem posed is impossible to solve. So what do we do?
Do something reasonably good and cross our fingers? Or what is your solution? Feel free to comment below.
Three partly working solutions
Currently, I have only 3 solutions to this fundamental problem.
- Keep pounding on the chip manufacturers to give board designers the data they really need
- Use evaluation boards to measure one device (often difficult to do), add a safety margin and cross my fingers
- Look at the chip package and try to figure out what frequency response the package offers the die with respect to power. Then use this to set an upper limit for where we have a chance to do something at the board-level? And cross my fingers that the manufacturer did what they needed to do for the higher frequencies on-chip and on-package.
None of these solutions are really good. Crossing fingers in engineering should never be “the right solution”. Doing measurements like shown in the video here is only part of the solution – you still need to know the max target PDN frequency.
A better solution
I think a better solution would be for the chip manufacturers, to simply specify a board-level target max PDN frequency along with the voltage requirements.
Would that be sufficient? Or what do you think? Voice your opinion below.