• Skip to primary navigation
  • Skip to main content
  • Skip to primary sidebar
  • Skip to footer

EE-Training

Knowledge Makes You Curious

  • Home
  • Training Courses
    • Signal Integrity to 56+Gbps with Hands-On Simulation
    • Open the Black Box of Memory
  • References
    • For Signal Integrity with Hands-On Simulation
    • For Lee Ritchey: Signal Integrity
    • For Lee Ritchey: Stackup Design
    • For SI Simulation Workshop
  • Blog
  • About
    • Contact Us
    • Terms & Conditions

What can go wrong in DDR interface designs?

September 22, 2015 by Rolf Østergaard

How many memory interface mistakes are there to make? There is one saying I like very much: ”Don’t make the same mistake twice”. There are enough mistakes to make that you probably don’t have time to try them all even once. In memory interface design there are still enough mistakes left to make… But just… Read more

Filed Under: Memory Interface Tagged With: ddr interface, DRAM mistakes, open the black box of memory, vref margin test

Start Learning Signal Integrity Today

Get a free book by Lee Ritchey (was $95) and news from EE-Training

PDNTool

Try pdntool.com and see how a 1-click optimizer might reduce your bypass caps.
Read more…

Jump to

Recent Posts

  • New PDN Tool to Optimize Bypass
  • The ultimate memory interface training course live in Copenhagen June 2-4, 2025
  • How we got un-hacked
  • Free IBIS Simulator: KiCAD 8?
  • Online memory course: Mar 1-5, 2021

Contact

EE-Training
Fruebjergvej 3
2100 Copenhagen
Denmark

Why

Training pays for itself.

The most expensive training
– is no training.

Rolf V. Østergaard

M.Sc.EE, SI Consultant
LinkedIn: Profile
Resume: CV (pdf)

Copyright © 2025 · EE-Training · Privacy Policy · CSR Policy · T&C
By using this site with cookies turned on in your bowser, you consent to cookies.