How much Bypass does the Zynq have On-chip?

So just how much bypass do you need for a Xilinx Zynq FPGA? Good question. It is quite obvious from looking at the chip itself that a significant amount of bypass is already implemented on the package itself. But how much is that exactly?

A simple ohmmeter test shows that four of the caps are connected to the 1.0V core voltage rail as shown here.

On top of what we can see on the package, there is most likely more on the die and in the package board itself. So how much is all that really doing for the impedance? The datasheet tells nothing about this. So let’s try to measure this (indirectly).

A client board with solid power and ground planes areas was stripped of all discrete bypass caps, so we could measure this. Well, actually we measure a combination of the package capacitance and the inter-plane capacitance of the power and ground planes. This is how the measurement setup looks – the board is connected to an R&S network analyzer (looking only at the 1.0V core voltage rail here):

The results with and without the bypass caps look like this (this is the network analyzer measurements you can do on pretty much any board set up for this as shown earlier):

As can be seen the package itself without any board level bypass is actually doing pretty good with both some high end and low end bypass already in place. The even higher frequencies may actually be handled at the die level also, but this is not measurable at the board level as the interconnecting inductance on the package may be too high.

The 23 capacitors (5x100uF, 6×4.7uF, 12×0.47uF) on the client board lowers the impedance almost a factor of 10x.

In order to dive a bit deeper the curve for the Zynq + board capacitance is plotted against a calculated parallel of 4 capacitances (you can try to do the same thing at PDNTool.com):

• The board capacitance (12nF)
• 3.5nF / 450pH / 60mOhm
• 11nF / 700pH / 70mOhm
• 3uF / 250pH / 8mOhm

It took a while to fiddle the numbers to find a reasonable fit, but I am pretty sure the fit here is fairly close. This is how well the two curves fit (the bluish curve is the calculated value, the green is the measured value):

The first three “dips” fit fairly nicely. The rest “goes crazy” in the measurement due to resonances in the board as expected.

I think it would be nice if Xilinx put this kind of information in the datasheet, but I haven’t fund that. Have you found any official numbers for this?

PS: On another site, John Larkin got curious the same way over 0.5uF on an Altera Arria FPGA. Compare this to the Zynq bypass.